![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=1920,fit=crop/mjEkB0VJBocKoqE0/oscilloscope_sine_square-AoPz2KkKa1fOW2xV.jpeg)
Signal reference
CIA#1
MOS 6526
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=600,h=1033,fit=crop/mjEkB0VJBocKoqE0/6526-m7VB7Zar2bhjEB9P.png)
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=382,h=658,fit=crop/mjEkB0VJBocKoqE0/6526-m7VB7Zar2bhjEB9P.png)
Pinout
Reference signals
Below are simple pictures of the different signals on the CIA#1 MOS 6526 chip which I use for reference/comparison during fault finding. For further details about the signals on the different C64 custom chips I will highly recommend Sven´s techsite. Information about the pinout is taken from: https://ist.uwaterloo.ca/~schepers/MJK/cia.html and https://www.c64-wiki.com/wiki/CIA.
Settings on Philips/Fluke PM3055 60 MHz analog oscilloscope:
2 V / DIV
See individual pictures for time settings
Signals have been measured on a working Commodore 64 assy 250466 in idle mode (blue screen).
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=288,h=176,fit=crop/mjEkB0VJBocKoqE0/pin01-dOq3WabbJVhLlzwa.jpeg)
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=382,h=233,fit=crop/mjEkB0VJBocKoqE0/pin01-dOq3WabbJVhLlzwa.jpeg)
Pin #1
VSS/GND
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=288,h=176,fit=crop/mjEkB0VJBocKoqE0/pin02-Yan3P1Br6vCzxak3.jpeg)
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=382,h=233,fit=crop/mjEkB0VJBocKoqE0/pin02-Yan3P1Br6vCzxak3.jpeg)
Pin #2
PA0
I/O-Port A Bit0 Bidirectional parallell port
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=288,h=176,fit=crop/mjEkB0VJBocKoqE0/pin03-A3QZg2JG7Jhr77yl.jpeg)
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=382,h=233,fit=crop/mjEkB0VJBocKoqE0/pin03-A3QZg2JG7Jhr77yl.jpeg)
Pin #3
PA1
I/O-Port A Bit1 Bidirectional parallell port
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=288,h=176,fit=crop/mjEkB0VJBocKoqE0/pin04-A85kPewlRKsPxQVK.jpeg)
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=382,h=233,fit=crop/mjEkB0VJBocKoqE0/pin04-A85kPewlRKsPxQVK.jpeg)
Pin #4
PA2
I/O-Port A Bit2 Bidirectional parallell port
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=288,h=176,fit=crop/mjEkB0VJBocKoqE0/pin05-YX4GKlyrn0i8Zyjb.jpeg)
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=382,h=233,fit=crop/mjEkB0VJBocKoqE0/pin05-YX4GKlyrn0i8Zyjb.jpeg)
Pin #5
PA3
I/O-Port A Bit3 Bidirectional parallell port
Ground.
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=288,h=176,fit=crop/mjEkB0VJBocKoqE0/pin06-Yg2g3jqq3bH1l7QE.jpeg)
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=382,h=233,fit=crop/mjEkB0VJBocKoqE0/pin06-Yg2g3jqq3bH1l7QE.jpeg)
Pin #6
PA4
I/O-Port A Bit4 Bidirectional parallell port
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=288,h=176,fit=crop/mjEkB0VJBocKoqE0/pin07-m7VBl33DbQULrROZ.jpeg)
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=382,h=233,fit=crop/mjEkB0VJBocKoqE0/pin07-m7VBl33DbQULrROZ.jpeg)
Pin #7
PA5
I/O-Port A Bit5 Bidirectional parallell port
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=288,h=176,fit=crop/mjEkB0VJBocKoqE0/pin08-AoPzjWJERBfGWwld.jpeg)
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=382,h=233,fit=crop/mjEkB0VJBocKoqE0/pin08-AoPzjWJERBfGWwld.jpeg)
Pin #8
PA6
I/O-Port A Bit6 Bidirectional parallell port
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=288,h=176,fit=crop/mjEkB0VJBocKoqE0/pin09-YBg5a7j5npUg7PDX.jpeg)
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=382,h=233,fit=crop/mjEkB0VJBocKoqE0/pin09-YBg5a7j5npUg7PDX.jpeg)
Pin #9
PA7
I/O-Port A Bit7 Bidirectional parallell port
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=288,h=176,fit=crop/mjEkB0VJBocKoqE0/pin10-meP0MxgZ5ecObb5x.jpeg)
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=382,h=233,fit=crop/mjEkB0VJBocKoqE0/pin10-meP0MxgZ5ecObb5x.jpeg)
Pin #10
PB0
I/O-Port B Bit0 Bidirectional parallell port
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=288,h=176,fit=crop/mjEkB0VJBocKoqE0/pin11-A85kPe84ggu7XJ0d.jpeg)
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=382,h=233,fit=crop/mjEkB0VJBocKoqE0/pin11-A85kPe84ggu7XJ0d.jpeg)
Pin #11
PB1
I/O-Port B Bit1 Bidirectional parallell port
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=288,h=176,fit=crop/mjEkB0VJBocKoqE0/pin12-Aq2zEWpgOeclZ07J.jpeg)
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=382,h=233,fit=crop/mjEkB0VJBocKoqE0/pin12-Aq2zEWpgOeclZ07J.jpeg)
Pin #12
PB2
I/O-Port B Bit2 Bidirectional parallell port
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=288,h=176,fit=crop/mjEkB0VJBocKoqE0/pin13-YKb2z3BL3of1bPeJ.jpeg)
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=382,h=233,fit=crop/mjEkB0VJBocKoqE0/pin13-YKb2z3BL3of1bPeJ.jpeg)
Pin #13
PB3
I/O-Port B Bit3 Bidirectional parallell port
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=288,h=176,fit=crop/mjEkB0VJBocKoqE0/pin14-dWxG4vNkQ7caMWwk.jpeg)
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=382,h=233,fit=crop/mjEkB0VJBocKoqE0/pin14-dWxG4vNkQ7caMWwk.jpeg)
Pin #14
PB4
I/O-Port B Bit4 Bidirectional parallell port
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=288,h=176,fit=crop/mjEkB0VJBocKoqE0/pin15-Yan3P1k18eU3e61O.jpeg)
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=382,h=233,fit=crop/mjEkB0VJBocKoqE0/pin15-Yan3P1k18eU3e61O.jpeg)
Pin #15
PB5
I/O-Port B Bit5 Bidirectional parallell port
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=288,h=176,fit=crop/mjEkB0VJBocKoqE0/pin16-mP4eJOkDznH4k0Jq.jpeg)
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=382,h=233,fit=crop/mjEkB0VJBocKoqE0/pin16-mP4eJOkDznH4k0Jq.jpeg)
Pin #16
PB6
I/O-Port B Bit6 Bidirectional parallell port
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=288,h=176,fit=crop/mjEkB0VJBocKoqE0/pin17-mv09NW6nbpcVn3l9.jpeg)
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=382,h=233,fit=crop/mjEkB0VJBocKoqE0/pin17-mv09NW6nbpcVn3l9.jpeg)
Pin #17
PB7
I/O-Port B Bit7 Bidirectional parallell port
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=288,h=176,fit=crop/mjEkB0VJBocKoqE0/pin18-YBg5a70yWRsyJXMy.jpeg)
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=382,h=233,fit=crop/mjEkB0VJBocKoqE0/pin18-YBg5a70yWRsyJXMy.jpeg)
Pin #18
/PC
Port control. Indicates availability of data on port B or both ports.
Note that there are some small periods where the signal is low.
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=288,h=176,fit=crop/mjEkB0VJBocKoqE0/pin19-mxB0W4PlVlSanMaB.jpeg)
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=382,h=233,fit=crop/mjEkB0VJBocKoqE0/pin19-mxB0W4PlVlSanMaB.jpeg)
Pin #19
TOD
Time of day. A TTL signal carrying the mains frequency (derived from the 9VAC) of 50Hz (PAL) / 60Hz (NTSC) is applied here to trigger the realtime clock.
Pin #20
VCC
Supply voltage (+5V DC).
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=288,h=176,fit=crop/mjEkB0VJBocKoqE0/pin20-meP0Mxz9WbtqjJXj.jpeg)
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=382,h=233,fit=crop/mjEkB0VJBocKoqE0/pin20-meP0Mxz9WbtqjJXj.jpeg)
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=288,h=176,fit=crop/mjEkB0VJBocKoqE0/pin21-m6LoRbVOxBCXLLel.jpeg)
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=382,h=233,fit=crop/mjEkB0VJBocKoqE0/pin21-m6LoRbVOxBCXLLel.jpeg)
Pin #21
/IRQ
Interrupt ReQuest. Becomes LOW when it matches a set bit in the interrupt control register on occurrence of the corresponding event. In the C64, this line is connected to the CPU's /IRQ pin (CIA #1) or to the /NMI pin (CIA #2), respectively.
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=288,h=176,fit=crop/mjEkB0VJBocKoqE0/pin22-meP0MJjOnaSEJgZb.jpeg)
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=382,h=233,fit=crop/mjEkB0VJBocKoqE0/pin22-meP0MJjOnaSEJgZb.jpeg)
Pin #22
R/W
Read/-Write. 0=read on data bus, 1=write on data bus.
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=288,h=176,fit=crop/mjEkB0VJBocKoqE0/pin23-A0x20jnRngHZwpxX.jpeg)
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=382,h=233,fit=crop/mjEkB0VJBocKoqE0/pin23-A0x20jnRngHZwpxX.jpeg)
Pin #23
/CS
Chip select. 0=coupled to data bus, 1=tri-state.
Chip Select - low level means active CIA.
Note that there are some small periods where the signal is low.
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=288,h=176,fit=crop/mjEkB0VJBocKoqE0/pin24-YZ9lGj5zj0IXP80N.jpeg)
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=382,h=233,fit=crop/mjEkB0VJBocKoqE0/pin24-YZ9lGj5zj0IXP80N.jpeg)
Pin #24
/FLAG
Negative edge IRQ input, can be used as handshake for either parallel port.
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=288,h=176,fit=crop/mjEkB0VJBocKoqE0/pin25-YBg5abqEwOIy45Vv.jpeg)
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=382,h=233,fit=crop/mjEkB0VJBocKoqE0/pin25-YBg5abqEwOIy45Vv.jpeg)
Pin #25
ø 2
Phi 2. System clock signal. All data bus action takes place only when ø2=1.
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=288,h=176,fit=crop/mjEkB0VJBocKoqE0/pin26-AQEGbZ0l1JsBE3jE.jpeg)
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=382,h=233,fit=crop/mjEkB0VJBocKoqE0/pin26-AQEGbZ0l1JsBE3jE.jpeg)
Pin #26
D7
Databus line D7
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=288,h=176,fit=crop/mjEkB0VJBocKoqE0/pin27-dOq3WD2bwefOG3zx.jpeg)
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=382,h=233,fit=crop/mjEkB0VJBocKoqE0/pin27-dOq3WD2bwefOG3zx.jpeg)
Pin #27
D6
Databus line D6
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=288,h=176,fit=crop/mjEkB0VJBocKoqE0/pin28-dWxG4OjDp3s43zge.jpeg)
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=382,h=233,fit=crop/mjEkB0VJBocKoqE0/pin28-dWxG4OjDp3s43zge.jpeg)
Pin #28
D5
Databus line D5
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=288,h=176,fit=crop/mjEkB0VJBocKoqE0/pin29-YX4GKx4x2Pfjan1k.jpeg)
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=382,h=233,fit=crop/mjEkB0VJBocKoqE0/pin29-YX4GKx4x2Pfjan1k.jpeg)
Pin #29
D4
Databus line D3
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=288,h=176,fit=crop/mjEkB0VJBocKoqE0/pin30-dOq3WD0xWQIZqerz.jpeg)
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=382,h=233,fit=crop/mjEkB0VJBocKoqE0/pin30-dOq3WD0xWQIZqerz.jpeg)
Pin #30
D3
Databus line D4
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=288,h=176,fit=crop/mjEkB0VJBocKoqE0/pin31-YNqZ629NpLILXR6n.jpeg)
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=382,h=233,fit=crop/mjEkB0VJBocKoqE0/pin31-YNqZ629NpLILXR6n.jpeg)
Pin #31
D2
Databus line D2
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=288,h=176,fit=crop/mjEkB0VJBocKoqE0/pin32-meP0MJOl11fgbx8y.jpeg)
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=382,h=233,fit=crop/mjEkB0VJBocKoqE0/pin32-meP0MJOl11fgbx8y.jpeg)
Pin #32
D1
Databus line D0
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=288,h=176,fit=crop/mjEkB0VJBocKoqE0/pin33-Yg2g3y7v5vi2KRVk.jpeg)
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=382,h=233,fit=crop/mjEkB0VJBocKoqE0/pin33-Yg2g3y7v5vi2KRVk.jpeg)
Pin #33
D0
Databus line D1
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=288,h=176,fit=crop/mjEkB0VJBocKoqE0/pin34-meP0MJ3XgRuw79XL.jpeg)
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=382,h=233,fit=crop/mjEkB0VJBocKoqE0/pin34-meP0MJ3XgRuw79XL.jpeg)
Pin #34
/RES
Reset input, low signal initiates CIA.
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=288,h=176,fit=crop/mjEkB0VJBocKoqE0/pin35-AoPzjJEprEiG8oWB.jpeg)
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=382,h=233,fit=crop/mjEkB0VJBocKoqE0/pin35-AoPzjJEprEiG8oWB.jpeg)
Pin #35
RS3
Register select #3. These four pins select one of the CIA's internal registers.
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=288,h=176,fit=crop/mjEkB0VJBocKoqE0/pin36-dWxG4Oe0EMiBvlK3.jpeg)
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=382,h=233,fit=crop/mjEkB0VJBocKoqE0/pin36-dWxG4Oe0EMiBvlK3.jpeg)
Pin #36
RS2
Register select #2. These four pins select one of the CIA's internal registers.
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=288,h=176,fit=crop/mjEkB0VJBocKoqE0/pin37-A85kPVZ7ZgCvr1e9.jpeg)
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=382,h=233,fit=crop/mjEkB0VJBocKoqE0/pin37-A85kPVZ7ZgCvr1e9.jpeg)
Pin #37
RS1
Register select #1. These four pins select one of the CIA's internal registers.
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=288,h=176,fit=crop/mjEkB0VJBocKoqE0/pin38-AVLGyazZ1RFNz72P.jpeg)
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=382,h=233,fit=crop/mjEkB0VJBocKoqE0/pin38-AVLGyazZ1RFNz72P.jpeg)
Pin #38
RS0
Register select #0. These four pins select one of the CIA's internal registers.
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=288,h=176,fit=crop/mjEkB0VJBocKoqE0/pin39-YBg5abyM48ca0N72.jpeg)
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=382,h=233,fit=crop/mjEkB0VJBocKoqE0/pin39-YBg5abyM48ca0N72.jpeg)
Pin #39
SP
Serial Port - bidirectional, internal shift register converts CPU parallel data into serial data and vice-versa.
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=288,h=176,fit=crop/mjEkB0VJBocKoqE0/pin40-AzGkbNDJ2XHWwg59.jpeg)
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=382,h=233,fit=crop/mjEkB0VJBocKoqE0/pin40-AzGkbNDJ2XHWwg59.jpeg)
Pin #40
CNT
Count - Internal timers can count pulses to this input. Can be used for frequency dependent operations.
Banner picture credits: Xato