![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=1920,fit=crop/mjEkB0VJBocKoqE0/oscilloscope_sine_square-AoPz2KkKa1fOW2xV.jpeg)
Signal reference
CIA#2
MOS 6526
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=600,h=1033,fit=crop/mjEkB0VJBocKoqE0/6526-m7VB7Zar2bhjEB9P.png)
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=382,h=658,fit=crop/mjEkB0VJBocKoqE0/6526-m7VB7Zar2bhjEB9P.png)
Pinout
Reference signals
Below are simple pictures of the different signals on the CIA#2 MOS 6526 chip which I use for reference/comparison during fault finding. For further details about the signals on the different C64 custom chips I will highly recommend Sven´s techsite. Information about the pinout is taken from: https://ist.uwaterloo.ca/~schepers/MJK/cia.html and https://www.c64-wiki.com/wiki/CIA.
Settings on Philips/Fluke PM3055 60 MHz analog oscilloscope:
2 V / DIV
See individual pictures for time settings
Signals have been measured on a working Commodore 64 assy 250466 in idle mode (blue screen).
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=288,h=176,fit=crop/mjEkB0VJBocKoqE0/pin01-mjE01R5ZgOfqJPQM.jpeg)
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=382,h=233,fit=crop/mjEkB0VJBocKoqE0/pin01-mjE01R5ZgOfqJPQM.jpeg)
Pin #1
VSS/GND
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=288,h=176,fit=crop/mjEkB0VJBocKoqE0/pin02-dOq3OQNKqQH0KzxD.jpeg)
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=382,h=233,fit=crop/mjEkB0VJBocKoqE0/pin02-dOq3OQNKqQH0KzxD.jpeg)
Pin #2
PA0
I/O-Port A Bit0 Bidirectional parallell port
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=288,h=176,fit=crop/mjEkB0VJBocKoqE0/pin03-m6LoENvr8GCvG114.jpeg)
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=382,h=233,fit=crop/mjEkB0VJBocKoqE0/pin03-m6LoENvr8GCvG114.jpeg)
Pin #3
PA1
I/O-Port A Bit1 Bidirectional parallell port
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=288,h=176,fit=crop/mjEkB0VJBocKoqE0/pin04-mnlzxM31JwsgvDD3.jpeg)
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=382,h=233,fit=crop/mjEkB0VJBocKoqE0/pin04-mnlzxM31JwsgvDD3.jpeg)
Pin #4
PA2
I/O-Port A Bit2 Bidirectional parallell port
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=288,h=176,fit=crop/mjEkB0VJBocKoqE0/pin05-mv09nq7z9qTna714.jpeg)
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=382,h=233,fit=crop/mjEkB0VJBocKoqE0/pin05-mv09nq7z9qTna714.jpeg)
Pin #5
PA3
I/O-Port A Bit3 Bidirectional parallell port
For CIA#2: ATN OUT [Serial bus]
Ground.
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=288,h=176,fit=crop/mjEkB0VJBocKoqE0/pin06-mjE01RvQ1zcMwK2k.jpeg)
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=382,h=233,fit=crop/mjEkB0VJBocKoqE0/pin06-mjE01RvQ1zcMwK2k.jpeg)
Pin #6
PA4
I/O-Port A Bit4 Bidirectional parallell port
For CIA#2: CLK OUT [Serial bus]
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=288,h=176,fit=crop/mjEkB0VJBocKoqE0/pin07-AzGkJQ3k6gu8g8ZP.jpeg)
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=382,h=233,fit=crop/mjEkB0VJBocKoqE0/pin07-AzGkJQ3k6gu8g8ZP.jpeg)
Pin #7
PA5
I/O-Port A Bit5 Bidirectional parallell port
For CIA#2: DATA OUT [Serial bus]
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=288,h=176,fit=crop/mjEkB0VJBocKoqE0/pin08-m7VB7W5RBWt4Lxw4.jpeg)
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=382,h=233,fit=crop/mjEkB0VJBocKoqE0/pin08-m7VB7W5RBWt4Lxw4.jpeg)
Pin #8
PA6
I/O-Port A Bit6 Bidirectional parallell port
For CIA#2: CLK IN [Serial bus]
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=288,h=176,fit=crop/mjEkB0VJBocKoqE0/pin09-mp8zj1Wq1DiVbln0.jpeg)
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=382,h=233,fit=crop/mjEkB0VJBocKoqE0/pin09-mp8zj1Wq1DiVbln0.jpeg)
Pin #9
PA7
I/O-Port A Bit7 Bidirectional parallell port
For CIA#2: DATA IN [Serial bus]
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=288,h=176,fit=crop/mjEkB0VJBocKoqE0/pin10-AwvXN69eDGHeqEEZ.jpeg)
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=382,h=233,fit=crop/mjEkB0VJBocKoqE0/pin10-AwvXN69eDGHeqEEZ.jpeg)
Pin #10
PB0
I/O-Port B Bit0 Bidirectional parallell port
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=288,h=176,fit=crop/mjEkB0VJBocKoqE0/pin11-mk30Bk6pJkIqo9j3.jpeg)
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=382,h=233,fit=crop/mjEkB0VJBocKoqE0/pin11-mk30Bk6pJkIqo9j3.jpeg)
Pin #11
PB1
I/O-Port B Bit1 Bidirectional parallell port
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=288,h=176,fit=crop/mjEkB0VJBocKoqE0/pin12-Yg2gZ0waE7T2P0Bp.jpeg)
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=382,h=233,fit=crop/mjEkB0VJBocKoqE0/pin12-Yg2gZ0waE7T2P0Bp.jpeg)
Pin #12
PB2
I/O-Port B Bit2 Bidirectional parallell port
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=288,h=176,fit=crop/mjEkB0VJBocKoqE0/pin13-AVLGvlj2L2iyWKQ0.jpeg)
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=382,h=233,fit=crop/mjEkB0VJBocKoqE0/pin13-AVLGvlj2L2iyWKQ0.jpeg)
Pin #13
PB3
I/O-Port B Bit3 Bidirectional parallell port
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=288,h=176,fit=crop/mjEkB0VJBocKoqE0/pin14-dJo83vQQrBF4OvG0.jpeg)
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=382,h=233,fit=crop/mjEkB0VJBocKoqE0/pin14-dJo83vQQrBF4OvG0.jpeg)
Pin #14
PB4
I/O-Port B Bit4 Bidirectional parallell port
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=288,h=176,fit=crop/mjEkB0VJBocKoqE0/pin15-mnlzxMKyk6fgjMgE.jpeg)
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=382,h=233,fit=crop/mjEkB0VJBocKoqE0/pin15-mnlzxMKyk6fgjMgE.jpeg)
Pin #15
PB5
I/O-Port B Bit5 Bidirectional parallell port
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=288,h=176,fit=crop/mjEkB0VJBocKoqE0/pin16-mv09nqKEDoIQ5Xa6.jpeg)
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=382,h=233,fit=crop/mjEkB0VJBocKoqE0/pin16-mv09nqKEDoIQ5Xa6.jpeg)
Pin #16
PB6
I/O-Port B Bit6 Bidirectional parallell port
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=288,h=176,fit=crop/mjEkB0VJBocKoqE0/pin17-AMqMBJ36rKUejkrW.jpeg)
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=382,h=233,fit=crop/mjEkB0VJBocKoqE0/pin17-AMqMBJ36rKUejkrW.jpeg)
Pin #17
PB7
I/O-Port B Bit7 Bidirectional parallell port
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=288,h=176,fit=crop/mjEkB0VJBocKoqE0/pin18-mP4exybNDlH4ky9l.jpeg)
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=382,h=233,fit=crop/mjEkB0VJBocKoqE0/pin18-mP4exybNDlH4ky9l.jpeg)
Pin #18
/PC
Port control. Indicates availability of data on port B or both ports.
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=288,h=176,fit=crop/mjEkB0VJBocKoqE0/pin19-AVLGvlv3oXHGx1Z8.jpeg)
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=382,h=233,fit=crop/mjEkB0VJBocKoqE0/pin19-AVLGvlv3oXHGx1Z8.jpeg)
Pin #19
TOD
Time of day. A TTL signal carrying the mains frequency (derived from the 9VAC) of 50Hz (PAL) / 60Hz (NTSC) is applied here to trigger the realtime clock.
Pin #20
VCC
Supply voltage (+5V DC).
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=288,h=176,fit=crop/mjEkB0VJBocKoqE0/pin20-YKb2eqeq0PuzqN67.jpeg)
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=382,h=233,fit=crop/mjEkB0VJBocKoqE0/pin20-YKb2eqeq0PuzqN67.jpeg)
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=288,h=176,fit=crop/mjEkB0VJBocKoqE0/pin21-dOq3OQL23bfpZbKr.jpeg)
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=382,h=233,fit=crop/mjEkB0VJBocKoqE0/pin21-dOq3OQL23bfpZbKr.jpeg)
Pin #21
/IRQ
Interrupt ReQuest. Becomes LOW when it matches a set bit in the interrupt control register on occurrence of the corresponding event. In the C64, this line is connected to the CPU's /IRQ pin (CIA #1) or to the /NMI pin (CIA #2), respectively.
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=288,h=176,fit=crop/mjEkB0VJBocKoqE0/pin22-AR0njGEvRMtjbokK.jpeg)
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=382,h=233,fit=crop/mjEkB0VJBocKoqE0/pin22-AR0njGEvRMtjbokK.jpeg)
Pin #22
R/W
Read/-Write. 0=read on data bus, 1=write on data bus.
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=288,h=176,fit=crop/mjEkB0VJBocKoqE0/pin23-m2WMxLD8oVFbvjkJ.jpeg)
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=382,h=233,fit=crop/mjEkB0VJBocKoqE0/pin23-m2WMxLD8oVFbvjkJ.jpeg)
Pin #23
/CS
Chip select. 0=coupled to data bus, 1=tri-state.
Chip Select - low level means active CIA.
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=288,h=176,fit=crop/mjEkB0VJBocKoqE0/pin24-meP0D9Zelpt5B3pL.jpeg)
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=382,h=233,fit=crop/mjEkB0VJBocKoqE0/pin24-meP0D9Zelpt5B3pL.jpeg)
Pin #24
/FLAG
Negative edge IRQ input, can be used as handshake for either parallel port.
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=288,h=176,fit=crop/mjEkB0VJBocKoqE0/pin25-m2WMxLLogBCVlb5V.jpeg)
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=382,h=233,fit=crop/mjEkB0VJBocKoqE0/pin25-m2WMxLLogBCVlb5V.jpeg)
Pin #25
ø 2
Phi 2. System clock signal. All data bus action takes place only when ø2=1.
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=288,h=176,fit=crop/mjEkB0VJBocKoqE0/pin26-m6LoENNypVIgD81O.jpeg)
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=382,h=233,fit=crop/mjEkB0VJBocKoqE0/pin26-m6LoENNypVIgD81O.jpeg)
Pin #26
D7
Databus line D7
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=288,h=176,fit=crop/mjEkB0VJBocKoqE0/pin27-ALpDQjj2PGfyXjR4.jpeg)
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=382,h=233,fit=crop/mjEkB0VJBocKoqE0/pin27-ALpDQjj2PGfyXjR4.jpeg)
Pin #27
D6
Databus line D6
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=288,h=176,fit=crop/mjEkB0VJBocKoqE0/pin28-dOq3Pjwxzntjv0a7.jpeg)
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=382,h=233,fit=crop/mjEkB0VJBocKoqE0/pin28-dOq3Pjwxzntjv0a7.jpeg)
Pin #28
D5
Databus line D5
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=288,h=176,fit=crop/mjEkB0VJBocKoqE0/pin29-Aq2zDx8PzvsboPx2.jpeg)
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=382,h=233,fit=crop/mjEkB0VJBocKoqE0/pin29-Aq2zDx8PzvsboPx2.jpeg)
Pin #29
D4
Databus line D3
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=288,h=176,fit=crop/mjEkB0VJBocKoqE0/pin30-YZ9lOD5X8zTk6gLx.jpeg)
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=382,h=233,fit=crop/mjEkB0VJBocKoqE0/pin30-YZ9lOD5X8zTk6gLx.jpeg)
Pin #30
D3
Databus line D4
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=288,h=176,fit=crop/mjEkB0VJBocKoqE0/pin31-mp8z2BN69OTL740q.jpeg)
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=382,h=233,fit=crop/mjEkB0VJBocKoqE0/pin31-mp8z2BN69OTL740q.jpeg)
Pin #31
D2
Databus line D2
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=288,h=176,fit=crop/mjEkB0VJBocKoqE0/pin32-mP4e86LaqVFVQvjW.jpeg)
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=382,h=233,fit=crop/mjEkB0VJBocKoqE0/pin32-mP4e86LaqVFVQvjW.jpeg)
Pin #32
D1
Databus line D0
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=288,h=176,fit=crop/mjEkB0VJBocKoqE0/pin33-Ylez97NqNRTVp2zD.jpeg)
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=382,h=233,fit=crop/mjEkB0VJBocKoqE0/pin33-Ylez97NqNRTVp2zD.jpeg)
Pin #33
D0
Databus line D1
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=288,h=176,fit=crop/mjEkB0VJBocKoqE0/pin34-m6Lo3VxKKBhyBxn3.jpeg)
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=382,h=233,fit=crop/mjEkB0VJBocKoqE0/pin34-m6Lo3VxKKBhyBxn3.jpeg)
Pin #34
/RES
Reset input, low signal initiates CIA.
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=288,h=176,fit=crop/mjEkB0VJBocKoqE0/pin35-AwvXB01NgDuZ9bJm.jpeg)
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=382,h=233,fit=crop/mjEkB0VJBocKoqE0/pin35-AwvXB01NgDuZ9bJm.jpeg)
Pin #35
RS3
Register select #3. These four pins select one of the CIA's internal registers.
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=288,h=176,fit=crop/mjEkB0VJBocKoqE0/pin36-AzGkxakDDpUJrWJ3.jpeg)
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=382,h=233,fit=crop/mjEkB0VJBocKoqE0/pin36-AzGkxakDDpUJrWJ3.jpeg)
Pin #36
RS2
Register select #2. These four pins select one of the CIA's internal registers.
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=288,h=176,fit=crop/mjEkB0VJBocKoqE0/pin37-AzGkxakqDeT8j5v6.jpeg)
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=382,h=233,fit=crop/mjEkB0VJBocKoqE0/pin37-AzGkxakqDeT8j5v6.jpeg)
Pin #37
RS1
Register select #1. These four pins select one of the CIA's internal registers.
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=288,h=176,fit=crop/mjEkB0VJBocKoqE0/pin38-Ylez97DlOoHZxQX9.jpeg)
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=382,h=233,fit=crop/mjEkB0VJBocKoqE0/pin38-Ylez97DlOoHZxQX9.jpeg)
Pin #38
RS0
Register select #0. These four pins select one of the CIA's internal registers.
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=288,h=176,fit=crop/mjEkB0VJBocKoqE0/pin39-AMqM9j2wMJtwrvg8.jpeg)
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=382,h=233,fit=crop/mjEkB0VJBocKoqE0/pin39-AMqM9j2wMJtwrvg8.jpeg)
Pin #39
SP
Serial Port - bidirectional, internal shift register converts CPU parallel data into serial data and vice-versa.
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=288,h=176,fit=crop/mjEkB0VJBocKoqE0/pin40-meP06WyZq9hkoJjL.jpeg)
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=382,h=233,fit=crop/mjEkB0VJBocKoqE0/pin40-meP06WyZq9hkoJjL.jpeg)
Pin #40
CNT
Count - Internal timers can count pulses to this input. Can be used for frequency dependent operations.
Banner picture credits: Xato