![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=1920,fit=crop/mjEkB0VJBocKoqE0/oscilloscope_sine_square-AoPz2KkKa1fOW2xV.jpeg)
Signal reference
PLA
MOS 906114-01
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=600,h=739,fit=crop/mjEkB0VJBocKoqE0/906114-01pla-AQEGqPab4es54VL5.png)
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=328,h=404,fit=crop/mjEkB0VJBocKoqE0/906114-01pla-AQEGqPab4es54VL5.png)
Pinout
Reference signals
Below are simple pictures of the different signals on the PLA MOS 906114-01 chip which I use for reference/comparison during fault finding. For further details about the signals on the different C64 custom chips I will highly recommend Sven´s techsite.
Settings on Philips/Fluke PM3055 60 MHz analog oscilloscope:
2 V / DIV
See individual pictures for time settings
Signals have been measured on a working Commodore 64 assy 250466 in idle mode (blue screen).
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=288,h=176,fit=crop/mjEkB0VJBocKoqE0/pin_01-Y4L35WNagaioe4MY.jpeg)
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=328,h=203,fit=crop/mjEkB0VJBocKoqE0/pin_01-Y4L35WNagaioe4MY.jpeg)
Pin #1
N.C.
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=288,h=176,fit=crop/mjEkB0VJBocKoqE0/pin_02-m6Lo7Q3ZJEUEnGBZ.jpeg)
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=328,h=198,fit=crop/mjEkB0VJBocKoqE0/pin_02-m6Lo7Q3ZJEUEnGBZ.jpeg)
Pin #2
A13
Connected to A13 of the address bus
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=288,h=176,fit=crop/mjEkB0VJBocKoqE0/pin_03-A1aDxqbkawHpB22p.jpeg)
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=328,h=201,fit=crop/mjEkB0VJBocKoqE0/pin_03-A1aDxqbkawHpB22p.jpeg)
Pin #3
A14
Connected to A14 of the address bus
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=288,h=176,fit=crop/mjEkB0VJBocKoqE0/pin_04-A3QZj6R2k1SBW1ZP.jpeg)
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=328,h=184,fit=crop/mjEkB0VJBocKoqE0/pin_04-A3QZj6R2k1SBW1ZP.jpeg)
Pin #4
A15
Connected to A15 of the address bus
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=288,h=176,fit=crop/mjEkB0VJBocKoqE0/pin_05-YKb2jG4ZXGSyN8wE.jpeg)
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=328,h=193,fit=crop/mjEkB0VJBocKoqE0/pin_05-YKb2jG4ZXGSyN8wE.jpeg)
Pin #5
VA14
Connected to #VA14 on VIC-II
Used for programming field-programmable parts and not connected internally for mask programmable parts
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=288,h=176,fit=crop/mjEkB0VJBocKoqE0/pin_06-dJo8Lgx5B9hPRbZn.jpeg)
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=328,h=185,fit=crop/mjEkB0VJBocKoqE0/pin_06-dJo8Lgx5B9hPRbZn.jpeg)
Pin #6
CHAREN
Connected to #CHAREN on I/O port of the 6510 CPU
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=288,h=176,fit=crop/mjEkB0VJBocKoqE0/pin_07-mp8zDLpwJ8FW5205.jpeg)
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=328,h=184,fit=crop/mjEkB0VJBocKoqE0/pin_07-mp8zDLpwJ8FW5205.jpeg)
Pin #7
HIRAM
Connected to #HIRAM on I/O port of the 6510 CPU
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=288,h=176,fit=crop/mjEkB0VJBocKoqE0/pin_08-YNqZ7ekolWilg2kk.jpeg)
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=328,h=190,fit=crop/mjEkB0VJBocKoqE0/pin_08-YNqZ7ekolWilg2kk.jpeg)
Pin #8
LORAM
Connected to #LORAM on I/O port of the 6510 CPU
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=288,h=176,fit=crop/mjEkB0VJBocKoqE0/pin_09-YBg5ZWR9kGs5z7G6.jpeg)
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=328,h=191,fit=crop/mjEkB0VJBocKoqE0/pin_09-YBg5ZWR9kGs5z7G6.jpeg)
Pin #9
CAS
Connected to #CAS on the VIC-II
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=288,h=176,fit=crop/mjEkB0VJBocKoqE0/pin_10-YrDzZ57r8ZsQk34z.jpeg)
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=328,h=195,fit=crop/mjEkB0VJBocKoqE0/pin_10-YrDzZ57r8ZsQk34z.jpeg)
Pin #10
ROMH
#ROMH
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=288,h=176,fit=crop/mjEkB0VJBocKoqE0/pin_11-m7VBvPZkkQS7GVZ6.jpeg)
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=328,h=194,fit=crop/mjEkB0VJBocKoqE0/pin_11-m7VBvPZkkQS7GVZ6.jpeg)
Pin #11
ROML
#ROML
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=288,h=176,fit=crop/mjEkB0VJBocKoqE0/pin_12-YbNeLkMLgpu55Xve.jpeg)
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=328,h=195,fit=crop/mjEkB0VJBocKoqE0/pin_12-YbNeLkMLgpu55Xve.jpeg)
Pin #12
I/O
#I/O
Not so easy to see but the signal is pulled low for a very short period regularly.
Video capture of signal here
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=288,h=176,fit=crop/mjEkB0VJBocKoqE0/pin_13-mk306ovpzXck2OxX.jpeg)
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=328,h=220,fit=crop/mjEkB0VJBocKoqE0/pin_13-mk306ovpzXck2OxX.jpeg)
Pin #13
GR/W
GR/#W, connected to #WE on the color RAM
This signal is pulled low for a very short period regularly - quite the same way as pin #12.
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=288,h=176,fit=crop/mjEkB0VJBocKoqE0/pin_14-YX4GnoV8p1FwbjOe.jpeg)
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=328,h=201,fit=crop/mjEkB0VJBocKoqE0/pin_14-YX4GnoV8p1FwbjOe.jpeg)
Pin #14
VSS
Ground (GND)
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=288,h=176,fit=crop/mjEkB0VJBocKoqE0/pin_15-YKb2jnKxG7T2gLG7.jpeg)
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=328,h=190,fit=crop/mjEkB0VJBocKoqE0/pin_15-YKb2jnKxG7T2gLG7.jpeg)
Pin #15
CHARROM
Connected to #CS1 on the #CHARROM
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=288,h=176,fit=crop/mjEkB0VJBocKoqE0/pin_16-m7VBv79z7rf4xRyl.jpeg)
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=328,h=204,fit=crop/mjEkB0VJBocKoqE0/pin_16-m7VBv79z7rf4xRyl.jpeg)
Pin #16
KERNAL
Connected to #CS on the #KERNAL ROM
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=288,h=176,fit=crop/mjEkB0VJBocKoqE0/pin_17-m6Lo7EQDyEfKNRNj.jpeg)
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=328,h=187,fit=crop/mjEkB0VJBocKoqE0/pin_17-m6Lo7EQDyEfKNRNj.jpeg)
Pin #17
BASIC
Connected to #CS on the #BASIC ROM
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=288,h=176,fit=crop/mjEkB0VJBocKoqE0/pin_18-YbNeLP0xL4IeojZq.jpeg)
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=328,h=198,fit=crop/mjEkB0VJBocKoqE0/pin_18-YbNeLP0xL4IeojZq.jpeg)
Pin #18
CASRAM
Connected to the #CAS pin on the DRAM
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=288,h=176,fit=crop,trim=0;30.89108910891089;0;30.89108910891089/mjEkB0VJBocKoqE0/pin_19-AGB7aDKX5yu08blq.jpeg)
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=328,h=190,fit=crop,trim=0;0;0;0/mjEkB0VJBocKoqE0/pin_19-AGB7aDKX5yu08blq.jpeg)
Pin #19
CE
Chip Enable
Pin #20
VA12
Connected to VA12 on VIC-II
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=288,h=176,fit=crop/mjEkB0VJBocKoqE0/pin_20-AVLG8eyQEvIXG4JY.jpeg)
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=328,h=210,fit=crop/mjEkB0VJBocKoqE0/pin_20-AVLG8eyQEvIXG4JY.jpeg)
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=288,h=176,fit=crop/mjEkB0VJBocKoqE0/pin_21-mjE0NVPnn3cgDzxv.jpeg)
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=328,h=197,fit=crop/mjEkB0VJBocKoqE0/pin_21-mjE0NVPnn3cgDzxv.jpeg)
Pin #21
VA13
Connected to VA13 on VIC-II
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=288,h=176,fit=crop/mjEkB0VJBocKoqE0/pin_21-mjE0NVPnn3cgDzxv.jpeg)
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=328,h=197,fit=crop/mjEkB0VJBocKoqE0/pin_21-mjE0NVPnn3cgDzxv.jpeg)
Pin #22
GAME
Connected to #GAME on pin 8 of cartridge port
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=288,h=176,fit=crop/mjEkB0VJBocKoqE0/pin_23-YlezlVvgEKC4enwa.jpeg)
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=328,h=186,fit=crop/mjEkB0VJBocKoqE0/pin_23-YlezlVvgEKC4enwa.jpeg)
Pin #23
EXROM
Connected #EXROM on pin 9 of cartridge port
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=288,h=176,fit=crop/mjEkB0VJBocKoqE0/pin_24-m5KeE0LXRZFx4WJN.jpeg)
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=328,h=193,fit=crop/mjEkB0VJBocKoqE0/pin_24-m5KeE0LXRZFx4WJN.jpeg)
Pin #24
R/W
Connected to R/#W of the bus
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=288,h=176,fit=crop/mjEkB0VJBocKoqE0/pin_25-ALpD5r2aMgFy8Men.jpeg)
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=328,h=193,fit=crop/mjEkB0VJBocKoqE0/pin_25-ALpD5r2aMgFy8Men.jpeg)
Pin #25
AEC
#AEC, connected to inverted version of AEC on the VIC-II
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=288,h=176,fit=crop/mjEkB0VJBocKoqE0/pin_26-YBg5ZKZeleTM4gDK.jpeg)
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=328,h=200,fit=crop/mjEkB0VJBocKoqE0/pin_26-YBg5ZKZeleTM4gDK.jpeg)
Pin #26
BA
Connected to BA on the VIC-II
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=288,h=176,fit=crop/mjEkB0VJBocKoqE0/pin_27-A3QZjk1vBkF5wll0.jpeg)
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=328,h=188,fit=crop/mjEkB0VJBocKoqE0/pin_27-A3QZjk1vBkF5wll0.jpeg)
Pin #27
A12
Connected to A12 of the address bus
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=288,h=176,fit=crop/mjEkB0VJBocKoqE0/pin_28-YZ9lZKKPrJi4WeyX.jpeg)
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=328,h=190,fit=crop/mjEkB0VJBocKoqE0/pin_28-YZ9lZKKPrJi4WeyX.jpeg)
Pin #28
VCC
+5V
Banner picture credits: Xato