VIC-II - MOS 6569 | Refurbished

Signal reference
VIC-II
MOS 6569

Pinout

Image credits: By Bill Bertram - Own work, CC BY 2.5, https://commons.wikimedia.org/w/index.php?curid=473295

Reference signals

Below are simple pictures of the different signals on the CPU MOS 6569R5 chip which I use for reference/comparison during fault finding. For further details about the signals on the different C64 custom chips I will highly recommend Sven´s techsite. Also there is a magnificent article about the VIC-II by Christian Bauer which I highly recommend if you are interested in learning the inner details of the VIC-II chip (http://www.zimmers.net/cbmpics/cbm/c64/vic-ii.txt).

Information about the pinout is taken from:

https://ist.uwaterloo.ca/~schepers/MJK/vic2.html and https://en.wikipedia.org/wiki/MOS_Technology_VIC-II

Settings on Philips/Fluke PM3055 60 MHz analog oscilloscope:

2 V / DIV
See individual pictures for time settings

Signals have been measured on a working Commodore 64 assy 250466 in idle mode (blue screen).

Pin #1
DB6

Pin #2
DB5

Data bus line #5

Pin #3
DB4

Data bus line #4

Pin #4
DB3

Data bus line #3

Pin #5
DB2

Data bus line #2

Data bus line #6

Pin #6
DB1

Data bus line #1

Pin #7
DB0

Data bus line #0

Pin #8
/IRQ

Interrupt ReQuest.
This pin is going LOW when an interrupt was toggled in the VIC-II.

There are four possible sources for an IRQ:

rasterline, lightpen, sprite-sprite collision and sprite-background collision

Pin #9
LP

LightPen.
A falling edge on this input causes an interrupt.

Pin #10
/CS

Chip Select.
HIGH=VIC-II is decoupled from bus.

Pin #11
R/W

Read/-Write. LOW=write to registers, HIGH=read from registers.

Pin #12
BA

ReaDY. When going LOW, the CPU waits after next read cycle for this line going HIGH again.

If this line is low during a read access, the processor stops with the address lines reflecting the current address being fetched. It is ignored during write accesses. In the C64, RDY is used to stop the processor if the VIC needs additional bus cycles for character pointer and sprite data accesses. It is connected to the BA signal on the VIC.

Pin #13
VDD

Reference voltage. This pin is connected to +12V DC (6567/69), or +5V DC (8562/65).

NOTE:
This is the 6569 chip in use. Therefore the VDD=12 V and the scope is set to 10 V / DIV

Pin #14
Color

Color output

Pin #15
S/LUM

Sync / Lumimance output

Pin #16
AEC

Address Enable Control. Directly connected with AEC of the CPU. When going LOW, the CPU puts its bus lines into high impedance state and is thus totally decoupled from the rest of the system, so that the VIC-II can take control over it.