![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=1920,fit=crop/mjEkB0VJBocKoqE0/oscilloscope_sine_square-AoPz2KkKa1fOW2xV.jpeg)
Signal reference
VIC-II
MOS 6569
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=600,h=1010,fit=crop/mjEkB0VJBocKoqE0/vic-ii-Aq2zV3zp8BfJNVva.png)
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=328,h=552,fit=crop/mjEkB0VJBocKoqE0/vic-ii-Aq2zV3zp8BfJNVva.png)
Pinout
Image credits: By Bill Bertram - Own work, CC BY 2.5, https://commons.wikimedia.org/w/index.php?curid=473295
Reference signals
Below are simple pictures of the different signals on the CPU MOS 6569R5 chip which I use for reference/comparison during fault finding. For further details about the signals on the different C64 custom chips I will highly recommend Sven´s techsite. Also there is a magnificent article about the VIC-II by Christian Bauer which I highly recommend if you are interested in learning the inner details of the VIC-II chip (http://www.zimmers.net/cbmpics/cbm/c64/vic-ii.txt).
Information about the pinout is taken from:
https://ist.uwaterloo.ca/~schepers/MJK/vic2.html and https://en.wikipedia.org/wiki/MOS_Technology_VIC-II
Settings on Philips/Fluke PM3055 60 MHz analog oscilloscope:
2 V / DIV
See individual pictures for time settings
Signals have been measured on a working Commodore 64 assy 250466 in idle mode (blue screen).
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=288,h=176,fit=crop/mjEkB0VJBocKoqE0/pin01-A0x2p5GQoRirgpK7.jpeg)
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=328,h=203,fit=crop/mjEkB0VJBocKoqE0/pin01-A0x2p5GQoRirgpK7.jpeg)
Pin #1
DB6
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=288,h=176,fit=crop/mjEkB0VJBocKoqE0/pin02-AMqMoeZNKzSjny6W.jpeg)
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=328,h=196,fit=crop/mjEkB0VJBocKoqE0/pin02-AMqMoeZNKzSjny6W.jpeg)
Pin #2
DB5
Data bus line #5
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=288,h=176,fit=crop/mjEkB0VJBocKoqE0/pin03-Aq2zV3gKZyHgBQab.jpeg)
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=328,h=196,fit=crop/mjEkB0VJBocKoqE0/pin03-Aq2zV3gKZyHgBQab.jpeg)
Pin #3
DB4
Data bus line #4
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=288,h=176,fit=crop/mjEkB0VJBocKoqE0/pin04-meP0V4K0oXc93pOE.jpeg)
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=328,h=195,fit=crop/mjEkB0VJBocKoqE0/pin04-meP0V4K0oXc93pOE.jpeg)
Pin #4
DB3
Data bus line #3
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=288,h=176,fit=crop/mjEkB0VJBocKoqE0/pin05-mjE0VlK31wHN8JEZ.jpeg)
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=328,h=182,fit=crop/mjEkB0VJBocKoqE0/pin05-mjE0VlK31wHN8JEZ.jpeg)
Pin #5
DB2
Data bus line #2
Data bus line #6
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=288,h=176,fit=crop/mjEkB0VJBocKoqE0/pin06-mxB0VLN7xvUyB415.jpeg)
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=328,h=190,fit=crop/mjEkB0VJBocKoqE0/pin06-mxB0VLN7xvUyB415.jpeg)
Pin #6
DB1
Data bus line #1
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=288,h=176,fit=crop/mjEkB0VJBocKoqE0/pin07-Y4L30zBrxDS5ka4Z.jpeg)
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=328,h=198,fit=crop/mjEkB0VJBocKoqE0/pin07-Y4L30zBrxDS5ka4Z.jpeg)
Pin #7
DB0
Data bus line #0
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=288,h=176,fit=crop/mjEkB0VJBocKoqE0/pin08-m5Ke0q32Z5iL7p3R.jpeg)
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=328,h=196,fit=crop/mjEkB0VJBocKoqE0/pin08-m5Ke0q32Z5iL7p3R.jpeg)
Pin #8
/IRQ
Interrupt ReQuest.
This pin is going LOW when an interrupt was toggled in the VIC-II.
There are four possible sources for an IRQ:
rasterline, lightpen, sprite-sprite collision and sprite-background collision
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=288,h=176,fit=crop/mjEkB0VJBocKoqE0/pin09-mxB0VLDpnatZGnBr.jpeg)
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=328,h=191,fit=crop/mjEkB0VJBocKoqE0/pin09-mxB0VLDpnatZGnBr.jpeg)
Pin #9
LP
LightPen.
A falling edge on this input causes an interrupt.
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=288,h=176,fit=crop/mjEkB0VJBocKoqE0/pin10-mp8zVZEzX7u8qyLk.jpeg)
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=328,h=197,fit=crop/mjEkB0VJBocKoqE0/pin10-mp8zVZEzX7u8qyLk.jpeg)
Pin #10
/CS
Chip Select.
HIGH=VIC-II is decoupled from bus.
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=288,h=176,fit=crop/mjEkB0VJBocKoqE0/pin11-m7VB06WMQVFbojwp.jpeg)
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=328,h=197,fit=crop/mjEkB0VJBocKoqE0/pin11-m7VB06WMQVFbojwp.jpeg)
Pin #11
R/W
Read/-Write. LOW=write to registers, HIGH=read from registers.
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=288,h=176,fit=crop/mjEkB0VJBocKoqE0/pin12-dWxGKZj0q3iBb0rV.jpeg)
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=328,h=200,fit=crop/mjEkB0VJBocKoqE0/pin12-dWxGKZj0q3iBb0rV.jpeg)
Pin #12
BA
ReaDY. When going LOW, the CPU waits after next read cycle for this line going HIGH again.
If this line is low during a read access, the processor stops with the address lines reflecting the current address being fetched. It is ignored during write accesses. In the C64, RDY is used to stop the processor if the VIC needs additional bus cycles for character pointer and sprite data accesses. It is connected to the BA signal on the VIC.
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=288,h=176,fit=crop/mjEkB0VJBocKoqE0/pin13-mxB0VPBG48TKbr10.jpeg)
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=328,h=190,fit=crop/mjEkB0VJBocKoqE0/pin13-mxB0VPBG48TKbr10.jpeg)
Pin #13
VDD
Reference voltage. This pin is connected to +12V DC (6567/69), or +5V DC (8562/65).
NOTE:
This is the 6569 chip in use. Therefore the VDD=12 V and the scope is set to 10 V / DIV
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=288,h=176,fit=crop/mjEkB0VJBocKoqE0/pin14-mk30Vb0V63Ir7paB.jpeg)
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=328,h=199,fit=crop/mjEkB0VJBocKoqE0/pin14-mk30Vb0V63Ir7paB.jpeg)
Pin #14
Color
Color output
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=288,h=176,fit=crop/mjEkB0VJBocKoqE0/pin15-A0x2pRo4qvfyEN2o.jpeg)
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=328,h=193,fit=crop/mjEkB0VJBocKoqE0/pin15-A0x2pRo4qvfyEN2o.jpeg)
Pin #15
S/LUM
Sync / Lumimance output
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=288,h=176,fit=crop/mjEkB0VJBocKoqE0/pin16-AMqMoRaVj0cpLvL2.jpeg)
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=328,h=190,fit=crop/mjEkB0VJBocKoqE0/pin16-AMqMoRaVj0cpLvL2.jpeg)
Pin #16
AEC
Address Enable Control. Directly connected with AEC of the CPU. When going LOW, the CPU puts its bus lines into high impedance state and is thus totally decoupled from the rest of the system, so that the VIC-II can take control over it.
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=288,h=176,fit=crop/mjEkB0VJBocKoqE0/pin17-YbNeVEZp6jUZqXRz.jpeg)
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=328,h=201,fit=crop/mjEkB0VJBocKoqE0/pin17-YbNeVEZp6jUZqXRz.jpeg)
Pin #17
PH0
Phi 0. The VIC-II outputs the system clock for the 6510.
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=288,h=176,fit=crop/mjEkB0VJBocKoqE0/pin18-AwvXolP26WiXE0E6.jpeg)
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=328,h=196,fit=crop/mjEkB0VJBocKoqE0/pin18-AwvXolP26WiXE0E6.jpeg)
Pin #18
/RAS
Row Address Strobe
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=288,h=176,fit=crop/mjEkB0VJBocKoqE0/pin19-meP0VznOM5t93MWp.jpeg)
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=328,h=198,fit=crop/mjEkB0VJBocKoqE0/pin19-meP0VznOM5t93MWp.jpeg)
Pin #19
CAS
Col Address Strobe
Pin #20
VSS
Ground (0V)
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=288,h=176,fit=crop/mjEkB0VJBocKoqE0/pin20-dWxGKZyeXPtpXD7V.jpeg)
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=328,h=192,fit=crop/mjEkB0VJBocKoqE0/pin20-dWxGKZyeXPtpXD7V.jpeg)
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=288,h=176,fit=crop/mjEkB0VJBocKoqE0/pin21-YZ9lJNOKp1TaaMKG.jpeg)
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=328,h=192,fit=crop/mjEkB0VJBocKoqE0/pin21-YZ9lJNOKp1TaaMKG.jpeg)
Pin #21
PHCL
Phi color. The color clock for the VIC-II. 14.31818 MHz for NTSC, 17.734472 MHz for PAL.
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=288,h=176,fit=crop/mjEkB0VJBocKoqE0/pin22-AMqMOwo4DZHg3ajR.jpeg)
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=328,h=193,fit=crop/mjEkB0VJBocKoqE0/pin22-AMqMOwo4DZHg3ajR.jpeg)
Pin #22
PHIN
Phi in. DOT CLOCK for the VIC-II. 8.18 MHz for NTSC, 7.88 MHz for PAL.
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=288,h=176,fit=crop/mjEkB0VJBocKoqE0/pin23-AGB7ZVeDXjf30pPm.jpeg)
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=328,h=195,fit=crop/mjEkB0VJBocKoqE0/pin23-AGB7ZVeDXjf30pPm.jpeg)
Pin #23
A11
Address bus line #11
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=288,h=176,fit=crop/mjEkB0VJBocKoqE0/pin24-AR0nEBR92Li5aob0.jpeg)
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=328,h=197,fit=crop/mjEkB0VJBocKoqE0/pin24-AR0nEBR92Li5aob0.jpeg)
Pin #24
A0 (A8)
Multiplexed address bus line A0 / A8
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=288,h=176,fit=crop/mjEkB0VJBocKoqE0/pin25-A0x2EKJL0ecp9DWQ.jpeg)
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=328,h=195,fit=crop/mjEkB0VJBocKoqE0/pin25-A0x2EKJL0ecp9DWQ.jpeg)
Pin #25
A1 (A9)
Multiplexed address bus line A1 / A9
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=288,h=176,fit=crop/mjEkB0VJBocKoqE0/pin26-m6Lo6Mn1WNTozPeg.jpeg)
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=328,h=197,fit=crop/mjEkB0VJBocKoqE0/pin26-m6Lo6Mn1WNTozPeg.jpeg)
Pin #26
A2 (A10)
Multiplexed address bus line A2 / A10
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=288,h=176,fit=crop/mjEkB0VJBocKoqE0/pin27-Y4L3q2RaGwuKp2DW.jpeg)
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=328,h=197,fit=crop/mjEkB0VJBocKoqE0/pin27-Y4L3q2RaGwuKp2DW.jpeg)
Pin #27
A3 (A11)
Multiplexed address bus line A3 / A11
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=288,h=176,fit=crop/mjEkB0VJBocKoqE0/pin28-mjE03xnO04UXyQnr.jpeg)
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=328,h=195,fit=crop/mjEkB0VJBocKoqE0/pin28-mjE03xnO04UXyQnr.jpeg)
Pin #28
A4 (A12)
Multiplexed address bus line A4 / A12
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=288,h=176,fit=crop/mjEkB0VJBocKoqE0/pin29-ALpDaL4MKnHGaoPB.jpeg)
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=328,h=192,fit=crop/mjEkB0VJBocKoqE0/pin29-ALpDaL4MKnHGaoPB.jpeg)
Pin #29
A5 (A13)
Address bus line A6
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=288,h=176,fit=crop/mjEkB0VJBocKoqE0/pin30-YBg5P16nyeUloBjX.jpeg)
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=328,h=195,fit=crop/mjEkB0VJBocKoqE0/pin30-YBg5P16nyeUloBjX.jpeg)
Pin #30
A6
Multiplexed address bus line A5 / A13
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=288,h=176,fit=crop/mjEkB0VJBocKoqE0/pin31-mp8zxGBJjPSw47oZ.jpeg)
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=328,h=192,fit=crop/mjEkB0VJBocKoqE0/pin31-mp8zxGBJjPSw47oZ.jpeg)
Pin #31
A7
Address bus line A7
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=288,h=176,fit=crop/mjEkB0VJBocKoqE0/pin32-Yg2gDkBqGXFEjyj6.jpeg)
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=328,h=195,fit=crop/mjEkB0VJBocKoqE0/pin32-Yg2gDkBqGXFEjyj6.jpeg)
Pin #32
A8
Address bus line A9
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=288,h=176,fit=crop/mjEkB0VJBocKoqE0/pin33-AoPzOyl6azTgG8vJ.jpeg)
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=328,h=192,fit=crop/mjEkB0VJBocKoqE0/pin33-AoPzOyl6azTgG8vJ.jpeg)
Pin #33
A9
Address bus line A8
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=288,h=176,fit=crop/mjEkB0VJBocKoqE0/pin34-meP08keNvQT5nVKo.jpeg)
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=328,h=200,fit=crop/mjEkB0VJBocKoqE0/pin34-meP08keNvQT5nVKo.jpeg)
Pin #34
A10
Address bus line A10
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=288,h=176,fit=crop/mjEkB0VJBocKoqE0/pin35-A85kJj3eWQF56V1E.jpeg)
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=328,h=192,fit=crop/mjEkB0VJBocKoqE0/pin35-A85kJj3eWQF56V1E.jpeg)
Pin #35
DB11
Data bus line #11
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=288,h=176,fit=crop/mjEkB0VJBocKoqE0/pin36-mjE03kEkeVfX2q2G.jpeg)
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=328,h=198,fit=crop/mjEkB0VJBocKoqE0/pin36-mjE03kEkeVfX2q2G.jpeg)
Pin #36
DB10
Data bus line #10
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=288,h=176,fit=crop/mjEkB0VJBocKoqE0/pin37-ALpDawp6WgFOy0aW.jpeg)
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=328,h=194,fit=crop/mjEkB0VJBocKoqE0/pin37-ALpDawp6WgFOy0aW.jpeg)
Pin #37
DB9
Data bus line #9
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=288,h=176,fit=crop/mjEkB0VJBocKoqE0/pin38-mnlzayk1EzCEoRyW.jpeg)
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=328,h=198,fit=crop/mjEkB0VJBocKoqE0/pin38-mnlzayk1EzCEoRyW.jpeg)
Pin #38
DB8
Data bus line #8
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=288,h=176,fit=crop/mjEkB0VJBocKoqE0/pin39-dJo81rOMKwi2MxX2.jpeg)
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=328,h=191,fit=crop/mjEkB0VJBocKoqE0/pin39-dJo81rOMKwi2MxX2.jpeg)
Pin #39
DB7
Data bus line #7
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=288,h=176,fit=crop/mjEkB0VJBocKoqE0/pin40-YD0a2nnVwGcyZaMK.jpeg)
![](https://assets.zyrosite.com/cdn-cgi/image/format=auto,w=328,h=197,fit=crop/mjEkB0VJBocKoqE0/pin40-YD0a2nnVwGcyZaMK.jpeg)
Pin #40
VCC
Supply voltage (+5V DC)
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